Processing of images with multirate digital filters is well known in the art, as exemplified by U.S. Pat. No. 4,852,035 and U.S. patent application No. 07/766,128. For example, it is well known to filter, re-size, project and warp images (see Wolberg, G. "Digital Image Warping", IEEE Computer Society Press 1988; Lim, J. S., "Two Dimensional Signal and Image Processing", Prentice Hall 1990; and Rabiner, L. R. "Multirate Digital Signal Processing", Prentice Hall, 1983). The use of these and other prior art image processing techniques is characterized by hardware architectures not suitable for efficient integrated circuit (IC) implementation.
One implementation of a digital decimating filter is the traditional approach of using the classical tapped delay FIR filter to realize a high order filter. For example to implement a 129 tap digital filter requires 128 delay elements. For horizontal processing, the delay elements are pixel delays. For vertical processing, the IC real estate penalty is more severe since the delay elements are line stores.